In data processing apparatus such as PCs, servers, graphics cards and mobile telephones, data are stored in semiconductor devices and processed by a memory controller. The data are transferred between the memory controller and the semiconductor devices assigned to the memory controller via a plurality of data signal lines arranged to form a data bus. The data transfer is controlled by the memory controller by means of control and address signal lines, which form a control bus and an address bus, respectively. The performance of a data processing apparatus is substantially determined by a transfer speed or data transfer rate at which the data are transferred on the data bus.
Higher data transfer rates are accompanied by an increase in the requirements made of the formation of the data signal lines and made of output drivers (off chip drivers, or OCDs) by output circuits of the semiconductor memory devices, which output, or drive, the data as data signals on the data bus. Since parasitic capacitances, inductances, resistances and reflection points formed in the course of the data signal lines, as well as circuits connected to the data bus can influence such features as delay and response times, edge gradient and data signal levels, it is desirable to characterize the output circuits in a test environment that simulates a later application as precisely as possible. A memory controller is usually required for the operation of the semiconductor memory device in the test environment.
Semiconductor memory devices and the memory controllers which control the semiconductor memory devices are developed largely in parallel. Therefore, the actual memory controllers with which the semiconductor memory devices are to be operated in an actual application may not be available during a characterization phase of the output drivers or output circuits of the semiconductor memory device. However, a test of the output drivers of the semiconductor memory devices that is close to the application requires a test environment with a memory controller that can operate the semiconductor devices in an environment close to the application.
Therefore, in conventional methods for characterizing output drivers of semiconductor memory devices in an environment close to the application, as is explained below with reference to FIG. 2, the semiconductor memory devices are operated by a test memory controller, while an application memory controller is only simulated passively.
FIG. 2 shows two semiconductor memory devices 1, containing output circuits 14 to be characterized. The semiconductor memory devices 1 are in each case connected to a test memory controller 21 via a control bus CMD and an address bus ADR. Output circuits 14 are in each case connected to a data signal terminal 13. The data bus DQ is connected to data signal terminals 13. In a switch position A of a switching device 24, the data bus DQ of semiconductor memory devices 1, of which an individual data signal DQ is illustrated, is connected to memory controller 21. In a switch position B of switching device 24, test memory controller 21 is disconnected from the data bus DQ of semiconductor memory devices 1. Instead, the data bus DQ is connected to a load simulation 23 via a connecting line 22. In this case, the load properties of connecting line 22 and load simulation 23 correspond to those of an application memory controller in an application.
For tests or for the characterization of output circuits 14, firstly, in the switch position A of the switching device 24, test data are written to memory cells 11, 12 of semiconductor memory devices 1 by means of test memory controller 21. Switching device 24 is switched over to position B and, via the control bus CMD and the address bus ADR, semiconductor memory device 1 is stimulated for outputting the test data at data signal terminals 13. In this case, test circuitry, comprising connecting line 22 and load simulation 23, simulates a later application with an application memory controller that is not yet available or can be programmed in complex fashion. By means of a measuring head 25, measurement signals are coupled out from the data signals DQ driven by output circuits 14 and are transferred to a test data evaluation device 26.
Such characterization of output circuits is necessary in particular for a semiconductor memory device with a double data rate interface (DDR-IF). In the case of semiconductor memory devices with a DDR-IF, data is transferred both upon the rising edge and upon the falling edge of a clock signal. The data transfer rate is thus doubled for the same clock frequency.
As illustrated in a simplified manner in FIG. 1, an output circuit 14 of a semiconductor memory device with a DDR-IF is simultaneously fed, at the input, a first data signal RDATA from a first memory cell 11 and a second data signal FDATA from a second memory cell 12. The data RDATA and FDATA are read from the memory cells 11, 12 synchronously with a clock signal CLK of the semiconductor memory device. Furthermore, a strobe signal STR is derived from the clock signal CLK. A strobe pulse is generated at STR essentially synchronously with each edge at CLK. The output signal of output circuit 14 is a data signal DQ, which is output at a data signal terminal 13 of the semiconductor memory device. The assignment of the data signal DQ to one of the two input signals RDATA or FDATA changes with each strobe pulse at STR.
One disadvantage of the test construction illustrated in FIG. 2 is the fact that writing access to a memory cell array with memory cells 11, 12 of semiconductor memory device 1 is necessary. This always requires at least temporary connection of the test memory controller 21 to the data bus DQ, whereby a result of a characterization measurement is corrupted, however. Moreover, switching device 24 for disconnecting test memory controller 21 or for connecting a load simulation 23 of an application memory controller already substantially alters the result of the characterization measurement.